X86 - Chronology | Technology Trends

Chronology

The table below lists brands of common consumer targeted processors implementing the x86 instruction set, grouped by generations that emphasize important events of x86 history. Note: CPU generations are not strict - each generation is characterized by significantly improved or commercially successful processor microarchitecture designs.

Generation	First introduced	Prominent consumer CPU brands	Linear/physical address space	Notable (new) features
1	1978	Intel 8086, Intel 8088 and clones	16-bit / 20-bit (segmented)	First x86 microprocessors
1	1982	Intel 80186, Intel 80188 and clones, NEC V20/V30	16-bit / 20-bit (segmented)	Hardware for fast address calculations, fast mul/div, etc.
2	1982	Intel 80286 and clones	16-bit (30-bit virtual) / 24-bit (segmented)	MMU, for protected mode and a larger address space.
3 (IA-32)	1985	Intel 80386 and clones, AMD Am386	32-bit (46-bit virtual) / 32-bit	32-bit instruction set, MMU with paging.
4 (FPU)	1989	Intel486 and clones, AMD Am486/Am5x86		RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache.
4/5	1997	IDT/Centaur-C6, Cyrix III-Samuel, VIA C3-Samuel2 / VIA C3-Ezra (2001), VIA C7 (2005)		In-order, integrated FPU, some models with on-chip L2 cache, MMX, SSE.
5	1993	Pentium, Pentium MMX, Cyrix 5x86, Rise mP6		Superscalar, 64-bit databus, faster FPU, MMX (2× 32-bit).
5/6	1996	AMD K5, Nx586 (1994)		μ-op translation.
6	1995	Pentium Pro, Cyrix 6x86, Cyrix MII, Cyrix III-Joshua (2000)	As above / 36-bit physical (PAE)	μ-op translation, conditional move instructions, Out-of-order, register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro).
	1997	AMD K6/-2/3, Pentium II/III		L3-cache support, 3DNow!, SSE (2× 64-bit).
	2003	Pentium M, Intel Core (2006)		optimized for low power.
7	1999	Athlon, Athlon XP		Superscalar FPU, wide design (up to three x86 instr./clock).
7	2000	Pentium 4		deeply pipelined, high frequency, SSE2, hyper-threading.
7/8	2000	Transmeta Crusoe, Efficeon		VLIW design with x86 emulator, on-die memory controller.
	2004	Pentium 4 Prescott	64-bit / 40-bit physical in first AMD implementation	Very deeply pipelined, very high frequency, SSE3, 64-bit capability (integer CPU) is available only in LGA 775 sockets.
	2006	Intel Core 2		64-bit (integer CPU), low power, multi-core, lower clock frequency, SSE4 (Penryn).
	2008	VIA Nano		Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption, very low power, adaptive power management.
8 (x86-64)	2003	Athlon 64, Opteron		x86-64 instruction set (CPU main integer core), on-die memory controller, hypertransport.
8/9	2007	AMD Phenom	As above / 48-bit physical for AMD Phenom	Monolithic quad-core, SSE4a, HyperTransport 3 or QuickPath, native memory controller, on-die L3 cache, modular.
	2008	Intel Core i3/i5/i7, AMD Phenom II
	2008	Intel Atom		In-order but highly pipelined, very-low-power, on some models: 64-bit (integer CPU), on-die GPU.
	2011	AMD Bobcat, Llano		Out-of-order, 64-bit (integer CPU), on-die GPU, low power (Bobcat).
9 (GPU)	2011	Intel Sandy Bridge/Ivy Bridge, AMD Bulldozer and Trinity		SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU.
9 (GPU)	2013	Intel Haswell		AVX2 and FMA3 instructions.
— (MIC pilot)	2012	Intel Xeon Phi (Larrabee)		Many Integrated Cores (62), In-order P54C with x86-64, Very wide vector unit, LRBni instructions (8× 64-bit)